SoC selection & benchmarking
We benchmark candidate silicon against your actual model and frame rate, not a datasheet number, measuring inference latency, sustained throughput and power draw before the schematic is drawn.
Embedded engineering, from silicon to a certified box.
We build custom AI compute hardware around SoCs and system-on-modules: carrier board, firmware, on-device inference and production hand-off, delivered as one accountable stack.
- SoC evaluation
- SOM integration
- Carrier board design
- BSP & secure boot
- On-device inference
- EMI / EMC & certification
One team owns the silicon, the board and the model
Most edge AI projects stall in the gap between a hardware vendor and a software vendor. Purview closes it. We select the SoC, integrate a proven system-on-module, design the carrier board around your I/O, bring up the BSP, quantise the models to run on the NPU, and hand over a unit that passes certification and can be manufactured at volume.
The practice sits inside our Hyderabad and Bangalore engineering centres, alongside the modem, connectivity, multimedia and automotive platform teams, so board bring-up, driver work and validation happen under one roof.
- Compute
- Arm application processors with integrated NPU / GPU / DSP, plus discrete accelerators where the workload needs them
- Form factor
- SOM on custom carrier, or full custom PCB where volume and cost justify it
- Operating systems
- Embedded Linux (Yocto / Buildroot), Android, RTOS
- Connectivity
- 5G / LTE / Cat-M, Wi-Fi 6, BLE, GNSS, CAN, RS-485, PoE
- Deliverable
- Schematics, layout, BOM, firmware, quantised models, test fixtures and production documentation
Why we build on modules
A system-on-module puts the hard part (processor, memory, storage, power management and the RF-sensitive routing) onto a pre-validated board that is already through compliance. Your product-specific work then lives on a carrier we design for it. You get a shorter path to first units and a supply chain that survives a component going end-of-life.
Carrier board design
Schematic capture, multi-layer layout, power tree, signal integrity and thermal budgeting around the module, with the connectors, sensors and radios your deployment actually needs.
Secure boot & firmware
Signed boot chains, key provisioning, encrypted storage, watchdogs and fail-safe A/B OTA, so a fleet in the field can be updated without a truck roll and without opening an attack surface.
Board support packages
Kernel, device tree, drivers and HAL work across embedded Linux, Yocto, Android and RTOS, the same discipline our platform teams apply to modem, multimedia and automotive programmes.
On-device model optimisation
Quantisation to INT8 / INT4, operator fusion, NPU delegate tuning and memory-bandwidth work, getting a model that ran on a workstation to hold real-time latency inside a fanless enclosure.
Validation & production
Bench and environmental test, EMI / EMC pre-scan, regulatory readiness, functional test fixtures and end-of-line scripts, run in our own validation labs and handed to your contract manufacturer.
Co-developed with our silicon and module partners
We do not resell reference designs. Each build is a joint engineering effort with the module and connectivity vendors, which is what keeps lead times, component availability and long-term supply commitments predictable across a multi-year deployment.
SOM PLATFORMS
ALPS LAB/Grinn
Module platforms and carrier co-design, with hardware bring-up support from prototype through to a manufacturable revision.
SILICON & SUPPLY
Avnet Silica
Component sourcing, silicon vendor access and supply-chain continuity, including lifecycle and end-of-life planning on long-deployment products.
CO-DEVELOPMENT
Quectel/Vitrium
Joint development on custom compute platforms, sharing design effort across the electronics and integration workstreams.
CONNECTIVITY
Quectel
Cellular, GNSS and short-range wireless modules with the certification and carrier-approval work that gets a connected device deployable.
Custom AI compute boxes we build
Each of these starts from the same platform: a module, a carrier designed for the deployment, and models that run on the device rather than in a data centre. What changes is the sensor mix, the enclosure and the inference workload.
Law enforcement traffic control
Roadside units that read plates, detect violations and flag vehicles of interest at the junction, with evidence packaged and signed on the device before it is ever transmitted.
Enterprise traffic control
Gate, yard and campus flow: vehicle identification, occupancy counting and barrier control that keeps working when the site link goes down, because the decision is made locally.
Asset monitoring & management
Tracking high-value assets across sites: RFID and BLE reads fused with GNSS and motion, so location, custody and condition are one record instead of three systems.
AI inventory kiosk for stores
A wall kiosk that identifies the person, reads tagged and barcoded stock automatically and takes a spoken entry for anything untagged, one accountable record of who moved what.
AI receptionist
Front-desk units that greet, verify and route visitors, print badges and notify the host, running speech and face matching on the box so visitor data never leaves the building.
Drone surveillance
Payload compute that detects, tracks and geolocates from the air within a strict size, weight and power budget, and keeps flying its pattern when the radio link drops.
Edge AI cameras
Cameras that carry their own inference: detection, classification and anomaly alerts computed in the housing, so only events cross the network instead of continuous video.
Proven where accuracy and uptime are the contract
For a global fulfilment operator we integrated LiDAR with a custom AI perception pipeline on industrial edge hardware, delivering precise 3D package measurement and centre-position tracking on a live production line, hardware and software as one accountable stack.
±2 mm
Spatial measurement accuracy
<100 ms
Inference latency
99.7%
Uptime in production
30+ FPS
Sustained throughput
2.5× accuracy
Against a software-only baseline on the same line.
17.5% lower TCO
Over three years, versus separate hardware and software vendors.
40% less effort
Development effort saved by owning both sides of the stack.
AI copilots for embedded engineering teams
A large embedded organisation carries a deep pool of repetitive, high-skill work: board bring-up, log triage, compliance review, test authoring. We build copilots on your own engineering history that take the time out of each one. Models are fine-tuned on your data and hosted inside your network; nothing leaves your estate.
Board bring-up copilot
Bring-up in days, not weeks
A retrieval-augmented copilot built over your BSP, MCAL and driver history. It suggests register configurations, pin muxing and device-tree diffs, and root-causes boot logs, taking cycle time out of every derivative silicon spin.
RAG + code embeddings · on-premLog triage agent
Field logs classified at intake
A fine-tuned classifier and retriever over your historical protocol logs and defect database. It tags the scenario, surfaces the closest matching historical change request and drafts a reproduction spec, so an engineer opens the ticket at sixty per cent rather than zero.
time-series + text classifiersSafety & compliance lint
Compliance checks inside the pull request
MISRA-C, AUTOSAR Adaptive and ISO 26262 guideline checks that run on every pull request, explain each finding in plain language and draft the fix. Rework comes out of safety review rather than piling up ahead of it.
rules + LLM explainersTest synthesis from specification
From requirement document to runnable script
Ingests functional requirement documents and IEEE, 3GPP or SAE specifications, then generates Python and XML test scripts targeting your existing bench and HIL frameworks. Human-in-the-loop review, and regression coverage rises without adding headcount.
spec ingestion · HIL frameworksHardware / software co-verification
Silicon and firmware in one loop
An agent that orchestrates emulator, FPGA and silicon runs, correlates RTL waveforms against firmware traces and proposes bisections when a regression opens, shortening the tail on bring-up sign-off, where every day counts against a tape-out date.
emulator · FPGA · siliconHow an engagement starts: a twelve-week proof of concept, then shadow mode alongside your engineers, then a measured productivity lift, then an embedded ODC. Every model is fine-tuned on your data and hosted in your own VPC.
Edge AI reference applications
Silicon vendors and OEMs win customers faster with a working reference application running on the actual part rather than a slide about it. We build them with small pods on a quarterly cadence, and hand over source, quantised models, a measured performance report and an SDK a customer engineering team can take straight to an OEM.
HANDSET
On-device multimodal assistant
Camera, microphone and screen-context assistant running entirely on the device through the vendor NPU runtime. Sub-500 ms response with no cloud call and no telemetry: quantised small language models, streaming speech recognition and on-device retrieval.
AUTOMOTIVE
Driver & occupant monitoring
A DMS and OMS reference stack on automotive compute platforms: drowsiness, gaze, seatbelt and child-presence detection, built against Euro NCAP and UN R151 requirements rather than retro-fitted to them later.
XR
Spatial AI sample
Real-time scene understanding, hand and eye tracking and passthrough object anchoring, packaged as a sample an OEM can ship, aligned to the AR and MR practice we already run.
COMPUTE
Performance-per-watt harness
A repeatable power and battery lab for Arm PC platforms: an ISV application suite, NPU utilisation dashboards and Windows-on-Arm regression runs that produce a number you can put in front of a customer.
INDUSTRIAL & IoT
Industrial vision reference
Defect, dimension and barcode inspection built on the edge-vision stack proven on a live fulfilment line, repackaged for industrial camera SoCs and reusable across warehousing OEMs.
MODEL ZOO
Quantised model pack
A curated, benchmark-verified model zoo (small language models, vision-language models, speech recognition, OCR and detection) with deployment recipes and hand-off notes written for customer engineering teams.
Realistic cadence: one reference application per quarter with a six-to-eight person pod. You get the source, the quantised models, a performance report and an OEM-ready SDK; production hardening follows as an ODC engagement.
The infrastructure behind the engineering
Edge hardware has to be tested under real radio conditions, connected back to something, and operated once it is in the field. Purview builds and runs that layer as well: private test networks, RAN engineering, round-the-clock operations, and the data centre floors the workloads report to.
Lab & test connectivity
- Private 5G test networks
- Device-farm backhaul
- Secure ODC links into customer networks
- eSIM management and MVNO
- RF and protocol test support
- Wi-Fi 6 campus and lab networks
Wireless & RAN engineering
- 5G and LTE engineering
- Open RAN (ORAN)
- CV2X and connected devices
- Private 5G for labs and plants
- Protocol and interoperability validation
- Field and regulatory readiness
Network operations
- 24×7 NOC and monitoring
- Smart hands — L1 / L2 / L3
- Observability and telemetry
- Capacity and lifecycle management
- SLA-based managed services
- Zero-trust, ISO 27001-aligned
Data centres, designed, built and operated
The same group that engineers the device can run the floor it reports to. Our flagship build is a 50 MW design-build in Hyderabad on a twenty-year hyperscaler lease, taken from feasibility through commissioning to ongoing operations under a capex-aware design discipline.
50 MW
Flagship design-build, Hyderabad
20 yr
Hyperscaler lease term
AI-READY DENSITY
- AI and HPC rack densities
- Liquid-cooling-ready designs
- Platform-flexible across accelerator stacks
- Traditional and next-generation workloads
- Hyperscaler-grade SLAs
SILICON & INFERENCE
- Rack-scale inference deployments
- Floors, power and operations for accelerator platforms
- Validation racks for data-centre silicon
- Labs, networks and data centre from one partner
How a build runs
A typical programme moves from a scoped feasibility study to production units. You can enter at any stage, including with an existing design that needs to be finished, re-costed or brought through certification.
Feasibility & silicon selection
Workload profiling, candidate SoC and module shortlist, power and thermal envelope, cost and lead-time model. Ends with a specification you can price.
Prototype on a reference platform
Your models running on the chosen module and dev carrier, with measured latency and throughput, proving the workload before any board is fabricated.
Carrier board & enclosure design
Schematic, layout, mechanical and thermal design, first article fabrication and bring-up against a written acceptance test.
Firmware, BSP & model integration
Kernel and driver work, secure boot, OTA, device management, and the inference pipeline tuned to hold real-time latency on the target.
Validation & certification
Environmental and EMI / EMC testing, regulatory and carrier approvals, field pilot and defect closure in our validation labs.
Production & sustaining
Manufacturing pack, test fixtures, end-of-line scripts, component lifecycle watch and a sustaining engineering line for the deployed fleet.
Tell us what the box has to do.
Send us the workload, the environment and the volume. We will come back with a silicon shortlist, a power and thermal envelope, and an honest view of what it costs to get to first units.